FLASH memory employing electrically-erasable programmable read-only memory (EEPROM) is widely used today. FLASH memory cells use a floating-gate transistor that has an electrically-insulated gate sandwiched between a control gate and a channel in the substrate between a source and a drain. Charge is injected into the floating gate through a thin tunneling oxide between the substrate and the floating gate. Since the floating gate is surrounded by insulators such as oxide, the charge remains on the floating gate after programming or erasure.
FLASH memory based on n-channel transistors are initially erased. The control gate is grounded and the Vpp programming voltage applied to the drain, reversing the electric field across the thin oxide, and causing electrons to tunnel from the floating gate to the drain. Removing electrons from the floating gate during erasure allows more of the electric field from the control gate to reach the channel during a read, increasing read current in the channel. The erased cells have full current drive and are considered a logic 1.
After erasing, the cell can be programmed by injecting electrons into the floating gate. A large, positive programming voltage Vpp is applied to the control gate, causing electrons in the channel to tunnel through the thin oxide to be captured by the floating gate. The increased negative change on the floating gate cancels some of the positive charge on the control gate, reducing the effective gate voltage reaching the channel, thus reducing channel current. A programmed cell is considered a logic 0.
Reading the state of the FLASH cell is performed by applying an intermediate voltage such as gate voltage Vg onto the control gate. The source is grounded and the drain is connected to a bit line that is sensed by a sense amplifier. When the cell is erased, the cell transistor draws current from the bit line to the grounded source, and the drop in bit-line voltage can be sensed. A programmed cell does not pull the bit-line voltage down, or at least not as quickly as the erased cell. A read operation can be performed to verify programming, and programming repeated should the cell not be programmed as much as desired.
Many FLASH memories simply program a binary 1 or 0 onto each FLASH-memory cell. This provides a wide noise margin. However, in more general cases of Multi-level Cells (MLC), the amount of charge stored on the floating gate is inherently an analog value having a range of possible values, say four, rather than just two (binary) values.
Multi-level cells have more than two logic states per memory cell. For example, a single memory cell storing two bits of information could have 4 logic states: the 11 (erased) state has the most current during a read, the 00 (fully-programmed) state has the least current, while states 01 and 10 have less current than the erased 11 state, but more current than the 00 state, with state 01 having less current than state 10 during a read. In general, a multi-level cell could have 2N states or logic levels, where N is the number of binary bits of data stored by the single cell.
FIG. 1 shows a prior-art FLASH memory with a multi-level FLASH cell. Address 30 is divided into row and column addresses and decoded to select FLASH cell 20. The row address is decided by row decoder 18, which selects a row of FLASH cells by driving a reading gate voltage onto the control gate of FLASH cell 20. Column decoder 16 selects one column bit line to connect to the sense amplifier. Drain bias circuit 14 can provide a pull-up bias to the selected bit line, and bias transistor 10 functions as a column load and acts as an active resistor to the bias circuit.
Comparators 22, 26 each receive on their inverting inputs the voltage on the sensing node between transistor 10 and drain bias circuit 14. This sensing node is pulled lower by current through FLASH cell 20 and column decoder 16 when FLASH cell 20 is erased, but little or no current is drawn from this sensing node when FLASH cell 20 is programmed. Intermediate states of FLASH cell 20 draw intermediate amounts of current from the sensing node.
Reference generator 12 generates 3 reference voltages VR1, VR2, VR3 that correspond to voltages on the sensing node that are between the four possible states of FLASH cell 20. The middle reference voltage VR2 is applied to the non-inverting input of first comparator 22 to generate the most-significant-bit (MSB), D1, that can be output on line 24. When the sensing node's voltage is below VR2, comparator 22 drives a 1 that is output as the MSB result (D1) by line 24.
The MSB result from first comparator 22 is fed back to reference generator 12. When the MSB result is 1, lower reference voltage VR1 is applied to the non-inverting input of second comparator 26. When the sensing node's voltage is below VR1, second comparator 26 drives a 1 that is output as the LSB result (D0) by line 28. The state of FLASH cell 20 is then 11, the fully-erased state that draws the most current from the bit lines and sensing node. When the sensing node's voltage is above VR1, second comparator 26 drives a 0 that is output as the least-significant-bit (LSB) result (D0) by line 28. The state of FLASH cell 20 is then 10, the partially-erased state that draws somewhat less current from the bit lines and sensing node than the fully-erased state.
When the MSB result fed back is 0, upper reference voltage VR3 is applied to the non-inverting input of second comparator 26. When the sensing node's voltage is below VR3, second comparator 26 drives a 1 that is output as the LSB result (D0) by line 28. The state of FLASH cell 20 is then 01, the partially-programmed state that draws somewhat more current from the bit lines and sensing node than the fully-programmed state, but less current than the partially-erased state 10. When the sensing node's voltage is above VR3, second comparator 26 drives a 0 that is output as the LSB result (D0) by line 28. The state of FLASH cell 20 is then 00, the fully-programmed state that draws the least current from the bit lines and sensing node than the fully-erased state.
FIG. 2 is a graph of 4 states of a multi-level cell and intermediate reference voltages. The control-gate voltage Vg required to turn on the FLASH cell is shown on the x-axis. A fully-programmed cell, state 00, has the most electrons in its floating gate, and thus requires the highest gate voltage to turn on to a specified channel current. A fully-erased cell, state 11, has the fewest electrons in its floating gate, and requires the smallest Vg to turn on. Plots of bit-line and sense-line voltages can be similar to this plot using Vg under certain biasing conditions.
Middle reference voltage VR2 is between partially-erased state 10 and partially-programmed state 01. Lower reference voltage VR1 is between erased states 11 and 10, while upper reference voltage VR3 is between programmed states 01 and 00. For example, when Vcc is 3.3 volts, VR1 could be 1.3 volts, VR2 is 2.3 volts, and VR3 is 2.7 volts.
The y-axis shows the cell's Vt (threshold voltage) state strength. The strength or safety margin of a Vt-state is greatest when the Vt is half-way between adjacent reference voltages. Upper and lower limits for each Vt-state may be specified. For example, erased state 11 is between lower limit VL0 and upper limit VU0. State 10 is between lower limit VL1 and upper limit VU1. Reference voltage VR1 is between upper limit VU0 of state 11 and lower limit VL1 of state 10. During programming or erasure, the FLASH cell Vt is targeted to fall between upper and lower limits of a desired state. This provides a small margin to the nearest reference voltage, such as a margin of VR1–VU0 for state 11.
FIG. 3 is a flowchart of a binary-search reference-voltage comparison for a multi-level FLASH cell. Initially the sensing node is compared to the middle reference voltage VR2, step 44, by the first comparator. When the sensing node is below VR2, the MSB is 1, when the sensing node is above VR2, the MSB is 0.
When the sensing node is below VR2, the lower reference voltage VR1 is applied to the second comparator for comparison to the sensing node, step 46. When the sensing node is below VR1, step 50, the state is 11; when the sensing node is above VR1, step 52, (but below VR2 from step 44), the state is 10.
When the sensing node is above VR2, the upper reference voltage VR3 is applied to the second comparator for comparison to the sensing node, step 48. When the sensing node is above VR3, step 56, the state is 00; when the sensing node is below VR3, step 54, (but above VR2 from step 44), the state is 01.
The voltage comparisons in step 44 by the first comparator must be performed before the voltage comparison of either step 46 or step 48 by the second comparator. This causes a delay of 2*Ts, where Ts is the sensing-comparator delay. When the number of states is 8, another level of comparison is required, for a total of 3 levels or a delay of 3*Ts. In general, for a FLASH cell storing N bits, having 2N possible states, an N-level comparison is needed, producing a comparison delay of N*Ts.
Variations in fabrication processes and aging of the device may cause shifts in the threshold of the FLASH cell transistors. These shifts can weaken the cell state strength by moving the cell closer to the next reference voltage. As more levels are squeezed into a fixed supply-voltage range, the allowable margins for these shifts decreases. Reference voltages may have to be adjusted for these shifts.
More precise programming are performed by applying successively higher Vpp programming voltages to cells. After each successively-higher programming, the cells are verified to see if a target sensing voltage is reached. Programming can continue with a higher programming voltage until the target is reached.
While the binary-search comparison of reference voltages to the sensing node is useful, the sequential nature of such comparison introduces more delays as the number of levels per cell increases. What is desired is a single-pass comparator for sensing among multiple levels of a multi-level FLASH-memory cell.